Senior Physical Design / Backend Engineer

Key Responsibilities • RTL-to-Netlist Implementation: Own and drive the synthesis process from RTL to gate-level netlist, managing advanced logic structuring, power gating, and scan-chain insertion. • Advanced Clock Tree Architecture: Architect and implement complex clock networks tailored for massive compute clusters, dynamically evaluating trade-offs between: • Standard automated Clock Tree Synthesis %28CTS%29 for standard control logic blocks. • Symmetrical H-Tree networks to minimize global latency and systematic skew across compute boundaries. • High-performance Clock Mesh configurations to drastically reduce local skew, clock jitter, and dynamic power fluctuations across high-frequency arithmetic pipelines. • Floorplanning & P&R Execution: Drive chip-level floorplanning, power grid distribution, advanced routing, and placement optimization for complex compute engines and high-speed subsystems. • ASIC Vendor & IP Management: Partner closely with the external ASIC vendor or foundry ecosystem to manage hardware deliverables, handle custom hard macro integration, align on physical design constraints, and navigate the technical tape-out path. • Timing & Physical Signoff: Own static timing analysis %28STA%29 constraint development, timing closure, power integrity optimization %28IR drop/EM mitigation%29, and physical verification %28DRC, LVS, ERC, DFM%29 across cutting-edge process nodes. • Advanced Technology Alignment: Implement physical constraints and routing rules supporting high-speed peripherals %28100G–1.6T Ethernet, PCIe Gen5/6/7, LPDDR6/HBM%29 and advanced packaging architectures %282.5D/3D IC, UCIe chiplets%29. • Cross-Functional Co-Design: Collaborate intensely with front-end RTL designers and architecture teams to evaluate physical constraints, providing microarchitectural feedback to resolve physical design bottlenecks early in the development lifecycle. Key Requirements & Qualifications • Education & Experience: Bachelor’s or Master’s degree in Electrical/Computer Engineering or a related field, with 5+ years of hands-on physical design and backend implementation experience. • Proven Tape-Out Track Record: Successful experience delivering complex, high-performance, multi-million gate SoCs through tape-out on advanced FinFET process nodes %28e.g., TSMC 7nm, 5nm, 3nm or similar%29. • Clock Network Expertise: Deep practical knowledge of designing, synthesizing, and debugging advanced clocking architectures. Proven experience handling skew, jitter, dynamic voltage drop %28DVD%29, and power distribution problems specifically related to H-Trees and Clock Meshes. • Expertise in P&R & Synthesis Tools: Expert-level mastery of industry-standard EDA physical design flows, specifically Synopsys Fusion Compiler/Innovus, Design Compiler NXT, PrimeTime, and Calibre. • ASIC Vendor Collaboration: Direct experience working extensively with major ASIC vendors %28e.g., TSMC, Samsung, Intel Foundry Services%29 or turnkey design services providers to resolve physical design rules and handoff requirements. • Advanced Signoff Competence: Deep technical knowledge of timing closure patterns, multi-voltage/power-gated designs %28UPF/CPF%29, and high-frequency routing techniques. • Startup Agility: Exceptional capability to thrive in a fast-paced, high-ambiguity startup environment. A pragmatic engineer who knows how to balance meticulous physical design optimization with aggressive tape-out schedules. • Automation & Scripting: Strong proficiency in Tcl, Python, or Perl to build, customize, and maintain physical design infrastructure and tool flows.