VLSI Digital Design Graduate Engineer

Description About the AI Division The AI Division is a unique and dedicated group within Ceva, driving innovation in Machine Learning and Generative AI architectures for edge devices and cloud inference. Our R&D domains span Neural Network Processors (NPU), Vision DSPs, and advanced AI algorithms for applications across smartphones, tablets, automotive, surveillance cameras and many more edge AI systems. We combine cutting-edge hardware IP design with embedded software and system-level solutions, enabling the next generation of intelligent and energy-efficient devices. About the role: This position is designed as an entry-level role for a recent graduate, to join a top notch Digital Design group leading the NPU development. Key Responsibilities Participate in the Architecture definition and exploration Own and lead Micro-architecture development Complete advanced Verilog/SV coding using advanced methodologies/procedures/AI tools. Participate in the Verification convergence of the RTL and demonstrate full accountability to the Design code Meet production ready quality from both Front End (functional and formal verification) and Back End perspective (Timing closure and Static Timing Analysis) within the project timeline. Requirements B.Sc. / M.Sc. in Electrical Engineering (recent graduate). Basic understanding of VLSI / ASIC / verification concepts (academic level is sufficient). Fluent English – mandatory for daily collaboration with global teams. Strong motivation to learn and grow in VLSI Digital Design domain Advantages: Exposure to Perl / TCL / Verilog/SV scripting Familiarity with version control (e.g., Git, Azure DevOps / TFS) Academic or internship experience with simulation, verification, or EDA tools Please include your GPA and attach your final grade sheet